1. Field of the Invention
This invention relates to an architecture, circuitry and method for testing one or more integrated circuits, each of which implements a test access port (xe2x80x9cTAPxe2x80x9d) such as the JTAG access port described in IEEE Std 1149.1. The test circuitry can place test signals in parallel upon an integrated circuit, shift the test signals through boundary scan cells while using the serialized boundary scan architecture, and thereafter dispatch the test results in parallel from the integrated circuit.
2. Description of the Related Art
Testing an integrated circuit can be performed in various ways. For example, the integrated circuit can be tested while in wafer form using test probe operation. Additionally, or alternatively, the integrated circuit can be tested after it is scribed and packaged. In either instance, sequential and/or combinatorial logic of the integrated circuit must be tested using input test data, generally referred to as xe2x80x9ctest vectors.xe2x80x9d Test vectors are supplied from a commercial test machine or automated test equipment (xe2x80x9cATExe2x80x9d). Alternatively, the test vectors can be provided from circuitry upon the integrated circuit. Such circuitry is often referred to as built in self test (xe2x80x9cBISTxe2x80x9d) circuitry. BIST circuitry may use a pseudo-random sequence generator to produce test vectors forwarded to the functional core logic of the integrated circuit.
BIST has been used successfully on a number of integrated circuits. However, BIST is difficult to use when testing arbitrary random logic, and requires adding significant test circuitry to the integrated circuit area. If BIST is not used and the test vectors are applied from an external ATE, it is desirable that the test vectors not only verify the integrated circuit operation but also the integrated circuit as it exists on a printed circuit board.
In the early 1990""s, a standard was developed and approved as IEEE Std. 1149.1 and 1149.1a, henceforth referred to as the JTAG standard. The JTAG standard was envisioned to allow testing of the integrated circuit after it had been assembled onto the printed circuit board. Moreover, the JTAG standard provided for testing numerous integrated circuits on the board as well as the interconnect of those circuits to the printed conductors of the board. In-system testing was therefore provided for testing the entire, assembled printed circuit board using pins associated with a test access port (xe2x80x9cTAPxe2x80x9d).
An integrated circuit that is JTAG compliant will have reserved a four or five signal TAP. If testing of the integrated circuit involves a boundary scan mechanism, then each integrated circuit also contains one or more boundary scan cells and a TAP controller for orchestrating signal flow within and through each of those cells.
FIG. 1 illustrates a printed circuit board 10 having multiple integrated circuits 12, 14, and 16 mounted thereon. For sake of brevity, only three integrated circuits are shown. However, it is recognized that a printed circuit board may embody certainly more than three integrated circuits. FIG. 1 also illustrates three input conductors 18 and three output conductors 20 associated with integrated circuit 14. Almost all integrated circuits are known to include more than three input conductors (or pins), and more than three output conductors (or pins). Therefore, FIG. 1 is used only as an abbreviated example so as not to unduly complicate the drawing.
Coupled between the input pins and the to-be-tested core logic 22 are respective boundary scan cells 24. Likewise boundary scan cells 26 are shown between core logic 22 and the output pins. Depending on the state of TAP controller 28, each boundary scan cell can either allow core logic 22 to be connected to external integrated circuits 12 and/or 16, or can enable boundary scan testing from a test data input conductor, TDI. TDI along with the test data output conductor TDO, the test mode select conductor TMS, and the test clock conductor TCK form four of possibly five pins attributed to TAP. TDI and TDO are daisy-chained through each boundary scan cell 24 and 26, and from integrated circuit to integrated circuit, whereas TCK and TMS are broadcast. Prior to entering the first of the daisy-chained integrated circuits, signals upon TDI, TDO, TMS, and TCK of the TAP are derived from an ATE.
In addition to boundary scan cells 24 and 26 attributed to each input/output pin, integrated circuit 14 also may include scan elements (SEs) 25 arranged internal to the circuit 14. Scan elements 25 are chained together and used for internal manufacturing testing of the core logic, for example. Scan elements 25 communicate with corresponding portions of the core logic 22. Each scan element may receive a bit, and shift that bit to the next scan element in the chain such that when the scan is complete, a multiple number of scan elements contain a rather large test vector comprising a plurality of bits. Thus, the scan elements may be rather numerous and may include more than one chain to facilitate design debug and manufacturing testing. Scan elements 25 are serially accessible from the TDI, TDO, TMS and TCK signals. The IEEE Std 1149.1 specification provides for multiple scan chains, some of which may be known to the integrated circuit manufacturer only. An example by which the scan elements 25 are used arise in programmable logic devices, and are expressed in various data sheets of manufacturers such as Cypress Semiconductor Corp.
Depending on what is placed into a scan chain, its length can be quite large. Shifting test information into or out of a rather long scan register chain can demand a lot of input and output cycles and associated vector memory on the ATE channels assigned to access the TAP pins of the integrated circuit under test. The IEEE Std 1149.1 makes known the use of bypass registers, or identification code (IDCODE) registers on dedicated chains within possibly numerous scan element chains that extend throughout an integrated circuit. While the boundary scan cells 24 and 26 can be parallel accessible through input/output pins, the internal scan elements 25 can only be accessed through the serial chain. Thus, the boundary scan cells may be deemed a specific implementation of the scan technique to test any core logic whatsoever, and scan elements are specific to the core logic across which they are chained together in serial fashion.
FIG. 2 illustrates in more detail the daisy-chaining of multiple integrated circuits 30 that are solder connected to surface-mount pads or vias of a printed circuit board 10. Depending on the number of integrated circuits having a TAP access, a single serialized test signal stream can be input throughout boundary scan cells 32a and 32b of each integrated circuit and thereafter placed in parallel within the core logic 34 of those integrated circuits. The test vectors are thereby said to be serially fed and parallel placed (i.e., scanned) into the functional core logic. Conversely, the test vectors can only be sent in series into the scan elements via TDI, and received from the scan elements in series via TDO. The ATE connected to TDI and TDO thereby not only produces the test vectors for testing the assembled printed circuit board, but also reads the test vector results. Details of the JTAG and TAP architecture are provided in the 1149.1 and 1149.1a specification. Further details of boundary scan systems and test vectors forward from an ATE to and from boundary scan cells are provided in U.S. Pat. Nos. 5,751,163 and 5,805,607 (both of which are herein incorporated by reference). It is noted that when describing the serial placement of test vectors into the boundary scan cells, serial placement of test vectors occurs within the internal scan elementsxe2x80x94the only difference being that the scan chain of the scan elements can in some instances be much longer than, and have more scan elements than, the boundary scan cells.
While the provisions of JTAG and generally the concept of serially feeding test data into a single input pin and reading those results from a single output pin has many advantages, it also presents numerous disadvantages. For example, applying serially fed test vectors from an ATE to a TDI pin requires a significant amount of test time. In order to apply all the necessary test vectors to a relatively large logic portion, the serially fed test vectors must be quite lengthy. Each test vector must be serially scanned from one boundary scan cell to the next and, of greater criticality, from one scan element to the next within a rather large scan chain. The serially fed test vector proceeds from one scan cell or scan element until it reaches the appropriate xe2x80x9cinputxe2x80x9d scan cell (or scan element) in the chain where it can then be applied to the core logic. Thereafter, an xe2x80x9coutputxe2x80x9d scan cell (or scan element) will receive the test result of that test vector where output shifting is further necessary to present the result as a serially fed output signal on the TDO conductor. Serially feeding test vectors and serially reading those test results is not only time consumptive, but also is limiting as to the type of ATE that can be used. Specifically, the ATE is limited to one which can serially feed rather large numbers of test vectors and serially read those test results on a small number of pins.
It would desirable to utilize any conventional ATE, and not simply those designed to forward serialized test vectors and read serialized test results. Conventional testers which forward test vectors in parallel and receive test results in parallel would advantageously speed up the overall test process while maximizing the available vector memory applied to the integrated circuit via multiple tester pins. The desired parallel-delivered and parallel-received test mechanism should beneficially operate within the constraints of the JTAG compliant integrated circuit and JTAG printed circuit board architecture by only slightly modifying the boundary scan circuitry of that architecture. The improved test architecture, circuitry, and method could therefore have broader applications to highly complex integrated circuit testing while using a relatively small parallel-delivered test vector table employed in many conventional, multiple-pin testers.
The problems outlined above are in large part solved by an architecture which can apply test vectors in parallel to one or more integrated circuits arranged on and connected to a printed circuit board. The integrated circuit can therefore be tested by accessing at least some, if not all, boundary scan cells and internal scan elements arranged within one or more scan chains. The scan chains of the integrated circuit are tested either before or after assembly on or apart from a printed circuit board by any tester which can deliver test vectors and/or receive test results across numerous pins or conductors. Parallel delivery and receipt of test vectors and test results to and from the boundary scan cells provides for ease by which the test vectors can be placed upon the scan elements arranged in one or more chains internal to the core logic. Parallel delivery and receipt greatly enhances the overall test time and minimizes the test vector memory access times of the ATE. Additionally, depending on the test mode used, test vectors can be placed from a parallel-fed ATE or a serial-fed ATE.
Parallel delivery and receipt of test information preferably occurs to any and all scanable storage elements configured upon the integrated circuit. The delivery mechanism may, if desired, advantageously use the JTAG and/or boundary scan architecture of the integrated circuit and/or board. Preferably, the parallel delivered test vectors are forwarded onto the input pins of the integrated circuit, captured by the boundary scan cells, and shifted between boundary scan cells to present a test signal having serialized test vectors. The serial test vectors can then be sent to the scan elements on the appropriate scan chain inside the core logic and/or integrated circuit
When the proper number of vectors have been shifted to the appropriate elements, an update latch within each scan element may be used to present its corresponding vector to a conductor extending from the scan element to the core logic circuitry. After the core logic has been tested, the test result is output and selected for transmission into a series of capture latches arranged near the output conductors of the core logic. The capture latches of the output scan elements perform similar to the capture latches of the input scan elements in that the capture latches will serialize the test results through a series of shift operations.
Included within the integrated circuit is a parallel/serial multiplexer that is responsive to whether the test vectors were sent from the ATE in parallel or serial fashion. In other words, the multiplexers determine whether the scan elements will receive parallel-driven test vectors via the boundary scan cells or will receive serial-driven test vectors. If presented serially, then the ATE would be connected to the TDI pin of the TAP. Otherwise, the ATE is connected to multiple pins of the integrated circuit that may or may not be connected to the printed circuit board. Application of the parallel-driven ATE to the multiple pins can occur through a bed-of-nails type test apparatus, for example. Another parallel/serial multiplexer may be used at or near the output pins of the integrated circuit and is configured based on whether the test results will be forwarded from the integrated circuit in parallel or in serial fashion. Thus, each integrated circuit preferably includes a pair of parallel/serial multiplexers. Depending on how those multiplexers are configured, either a serial test mechanism or a parallel test mechanism can be used, with selectivity therebetween.
According to one embodiment, test architecture is provided. The architecture includes an integrated circuit having a logic portion (i.e., core logic), and a plurality of input pins adapted to receive a parallel delivered test signal. A plurality of capture latches may be configured to receive the test signal in serial fashion and to deliver the test signal to a plurality of update latches. Conductors within the core logic portion are coupled to receive the test signal in parallel fashion from each of the plurality of update latches. The capture latches and update latches are thereby associated with any scanable device linked together in serial fashion, including the boundary scan cells or the scan elements.
The logic portion can also deliver test results to a plurality of capture latches, whereby those latches are clocked so as to serialize the test results for serial read out through the TDO pin. Alternatively, the test results can be delivered, either directly or from the TDO through serial-to-parallel conversion, upon a plurality of output pins of the integrated circuit.
A test access port (TAP) controller is also provided. The controller includes a first control signal generator, a first clock signal generator, and a second control signal generator. Each of the generators are operably coupled to boundary scan cells and scan elements of an associated integrated circuit. The first control signal generator is adapted to capture a parallel delivered test signal and the first clock signal generator is adapted to shift the captured test signal onto a single conductor as a serial test signal. The second control signal generator can then disburse in parallel format the test information from the serial test signal onto separate conductors. The separate conductors are those which extend into the core logic (if the controller is controlling input boundary scan cells), or the separate conductors are output pins if the controller is used to control output boundary scan cells.
A method is also provided for testing an integrated circuit or circuit board containing multiple integrated circuits. The method includes applying a test signal to a plurality of input pins of an integrated circuit. The test signal may then be shifted upon a single conductor, whereupon a plurality of test signals are drawn from the single conductor and forwarded to combinatorial and sequential logic preferably within the core logic portion of the integrated circuit. The test signal applied to the plurality of input pins can be selected rather than a test signal applied to a TAP serial input conductor of the integrated circuit. Test results of the test signal upon the core logic may then be forwarded to a plurality of output pins, or to a single TAP serial output conductor of the integrated circuit. Parallel-driven test vectors from the ATE can be written into any scanable device (i.e., scan cell or scan element), and test results can be drawn from the scanable devices in parallel via the output pins of the integrated circuit. The scanable device may or may not have direct access to the integrated circuit input/output pins depending on whether the scanable devices are scan cells external to the core logic or scan elements internal to the core logic. Parallel-placement of the test vectors occur using primarily the already available boundary scan elements on a boundary scan portion of the integrated circuit.